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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT160 Presettable synchronous BCD decade counter; asynchronous reset
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
FEATURES * Synchronous counting and loading * Two count enable inputs for n-bit cascading * Positive-edge triggered clock * Asynchronous reset * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT160 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT160 are synchronous presettable decade counters which feature an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset to a HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = 0 V; Tamb= 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL propagation delay CP to Qn CP to TC MR to Qn MR to TC CET to TC propagation delay CP to Qn CP to TC CET to TC maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 39 34 pF CONDITIONS HC CL = 15 pF; VCC = 5 V 19 21 21 21 14 19 21 14 61 3.5 HCT 21 24 23 26 14 21 20 7 31 3.5 ns ns ns ns ns ns ns ns MHz pF UNIT Notes
74HC/HCT160
input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to LOW level regardless of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: 1 fmax = -------------------------------------------------------------------------------------------------------t P ( max ) ( CP to TC ) + t SU (CEP to CP)
1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V
tPLH
fmax CI CPD
December 1990
2
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PIN DESCRIPTION PIN NO. 1 2 3, 4, 5, 6 7 8 9 10 14, 13, 12, 11 15 16 SYMBOL MR CP D0 to D3 CEP GND PE CET Q0 to Q3 TC VCC NAME AND FUNCTION asynchronous master reset (active LOW) clock input (LOW-to-HIGH, edge-triggered) data inputs count enable input ground (0 V) parallel enable input (active LOW) count enable carry input flip-flop outputs terminal count output positive supply voltage
74HC/HCT160
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
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Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
74HC/HCT160
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS OPERATING MODE MR reset (clear) parallel load count hold (do nothing) Notes 1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH). H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition X = don't care = LOW-to-HIGH CP transition L H H H H H CP X X X CEP X X X h I X CET X X X h X I PE X I I h h h Dn X I h X X X Qn L L H count qn qn TC L L
(1) (1) (1)
OUTPUTS
L
December 1990
4
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
74HC/HCT160
Fig.6 Fig.5 State diagram.
Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two and three; inhibit.
Fig.7 Logic diagram.
December 1990
5
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH propagation delay CP to Qn propagation delay CP to TC propagation delay MR to Qn propagation delay MR to TC propagation delay CET to TC output transition time 61 22 18 69 25 20 69 25 20 69 25 20 47 17 14 19 7 6 80 16 14 80 16 14 100 20 17 80 16 14 135 27 23 22 8 6 28 10 8 30 11 9 22 8 6 41 15 12 -40 to +85 max. min. max. 185 37 31 215 43 31 210 42 36 220 44 37 150 30 26 75 15 13 100 20 17 100 20 17 125 25 21 100 20 17 170 34 29 230 46 39 270 54 46 265 53 45 275 55 47 190 38 33 95 19 16 120 24 20 120 24 20 150 30 26 120 24 20 205 41 35 -40 to +125 min. max. 280 56 48 325 65 55 315 63 54 330 66 56 225 45 38 110 22 19 ns
74HC/HCT160
TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig. 8
tPHL/ tPLH
ns
Fig. 8
tPHL
ns
Fig. 9
tPHL
ns
Fig. 9
tPHL/ tPLH
ns
Fig. 10
tTHL/ tTLH
ns
Figs 8 and 10
tW
clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time Dn to CP set-up time PE to CP
ns
Fig. 8
tW
ns
Fig. 9
trem
ns
Fig. 9
tsu
ns
Fig. 11
tsu
ns
Fig. 11
December 1990
6
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
Tamb (C) 74HC SYMBOL PARAMETER +25 min. typ. tsu set-up time CEP, CET to CP hold time Dn to CP hold time PE to CP hold time CEP, CET to CP maximum clock pulse frequency 200 40 34 0 0 0 0 0 0 0 0 0 6.0 30 35 63 23 18 -17 -6 -5 -41 -15 -12 -58 -21 -17 18 55 66 -40 to +85 max. min. max. 250 50 43 0 0 0 0 0 0 0 0 0 4.8 24 28 -40 to +125 min. 300 60 51 0 0 0 0 0 0 0 0 0 4.0 20 24 max. ns
74HC/HCT160
TEST CONDITIONS WAVEFORMS UNIT V CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig. 12
th
ns
Figs 11 and 12
th
ns
Figs 11 and 12
th
ns
Figs 11 and 12
fmax
MHz
Fig. 8
December 1990
7
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT160
The value of additional quiescent supply current (ICC) for unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT MR CP CEP Dn CET PT
UNIT LOAD COEFFICIENT 0.95 0.80 0.25 0.25 1.05 0.30
December 1990
8
Philips Semiconductors
Product specification
Presettable synchronous BCD decade counter; asynchronous reset
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tPHL tPLH tPHL tPHL tPHL tPLH tTHL/ tTLH tW tW trem tsu tsu tsu th th th fmax propagation delay CP to Qn propagation delay CP to TC propagation delay CP to TC propagation delay MR to Qn propagation delay MR to TC propagation delay CET to TC propagation delay CET to TC output transition time clock pulse width HIGH or LOW master reset pulse width LOW removal time MR to CP set-up time Dn to CP set-up time PE to CP set-up time CEP, CET to CP hold time Dn to CP hold time PE to CP hold time CEP, CET to CP maximum clock pulse frequency 16 20 20 18 30 50 0 0 0 16 25 28 23 27 30 17 9 7 8 11 9 10 18 30 -8 -13 -21 28 -40 to +85 max. min. max. 43 48 39 50 50 35 17 15 20 25 25 25 44 63 0 0 0 13 54 60 49 63 63 44 21 19 24 30 30 30 53 75 0 0 0 11 -40 to +125 min. max. 65 72 59 75 75 53 26 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
74HC/HCT160
TEST CONDITIONS WAVEFORMS UNIT V CC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig. 8 Fig. 8 Fig. 8 Fig. 9 Fig. 9 Fig. 10 Fig. 10 Figs 8 and 10 Fig. 8 Fig. 9 Fig. 9 Fig. 11 Fig. 11 Fig. 12 Figs 11 and 12 Figs 11 and 12 Figs 11 and 12 Fig. 8
MHz
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 9

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